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E2A0009-16-X1
Semiconductor MSM6926/6946
Semiconductor 300 bps Single Chip FSK MODEM
This version: Jan. 1998 MSM6926/6946 Previous version: Nov. 1996
GENERAL DESCRIPTION
The MSM6926 and the MSM6946 are OKI's 300 bps single chip modem series which transmit and receive serial, binary data over a switched telephone network using frequency shift keying (FSK). The MSM6926 is compatible with ITU-T V.21 series data sets, while the MSM6946 is compatible with Bell 103 series data sets. These devices provide all the necessary modulation, demodulation, and filtering required to implement a serial, asynchronous communication link. OKI's single chip modem series is designed for users who are not telecommunication experts and are easy to use cost effective alternative to standard discrete modem design. CMOS LSI technology provides the advantages of small size, low power, and increased reliability. The design of the integrated circuit assures compatibility with a broad base of installed low speed modems and acoustic couplers. Applications include interactive terminals, desk top computers, point of sale equipment, and credit verification systems.
FEATURES
* Compatible with ITU-T V.21 (MSM6926) * Compatible with BELL 103 (MSM6946) * CMOS silicon gate process * Switched capacitor and advanced CMOS analog technology * Data rate from 0 to 300 bps * Full duplex (2-Wire) * Originate and Answer modes * Selectable built-in timers and external delay timers possible * All filtering, modulation, demodulation, and DTE interface on chip * TTL compatible digital interface * Low power dissipation: 90 mW Typ. * Package options: 28-pin plastic DIP (DIP28-P-600-2.54) (Product name: MSM6926RS) (Product name: MSM6946RS) 44-pin plastic QFP (QFP44-P-910-0.80-K) (Product name: MSM6926GS-K) (Product name: MSM6946GS-K) (QFP44-P-910-0.80-2K) (Product name: MSM6926GS-2K) (Product name: MSM6946GS-2K)
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Semiconductor
MSM6926/6946
BLOCK DIAGRAM
SG1 VA VD AG DG AIN Receive Filter Demodulator Carrier Detect VA AG SG1 SG2 VREF
SG2 CDR2 CDR1 CD1
RD1
M FT
SW ROM
Cont.
RD2 CD2
AO
Transmit Filter
Modulator
DTE Interface
RD XD
X1 OSC X2 CLK TS1 Delay TS2 Clock Gen. Loop Test
RS1 RS2 CS CC LT
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Semiconductor
MSM6926/6946
PIN CONFIGURATION (TOP VIEW)
X1 1 X2 2 CLK 3 LT 4 CC 5 CS 6 RS1 7 RS2 8 XD 9 RD 10 CD1 11 CD2 12 RD1 13 RD2 14 28-Pin Plastic DIP
28 TS2 27 TS1 26 VD 25 AO 24 VA 23 FT 22 M 21 AIN 20 SG1 19 AG 18 SG2 17 CDR2 16 CDR1 15 DG
44 LT 43 CLK
36 TS1 35 VD CDR1 20 CDR2 21
38 TS2 37 NC
39 VA*
40 NC
42 X2 41 X1
34 AO
NC 1 CC 2 CS 3 RS1 4 NC 5 NC 6 NC 7 RS2 8 XD 9 RD 10 NC 11
CD1 12 CD2 13 RD1 14 NC 15 RD2 16 VA* 17 SG2 22 NC 18 DG 19
33 VA 32 FT 31 M 30 NC 29 NC 28 NC 27 NC 26 AIN 25 NC 24 SG1 23 AG
44-Pin Plastic QFP
Note:
*: Both No. 17 pin and No. 39 pin are set to be at VA level by setting No. 33 pin at VA level. NC: No connect pin
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Semiconductor
MSM6926/6946
PIN DESCRIPTIONS
Power
Pin No. RS GS-K 15 19 24 26 19 23 33 35
Name DG AG VA VD
I/O -- -- -- --
Description Ground reference of VD (digital ground) Ground reference of VA (digital ground) Supply voltage (+12 V nominal) Supply voltage (+5 V nominal)
Clocks
Pin No. RS GS-K 1 2 3 41 42 43
Name X1 X2 CLK
I/O -- -- O
Description Master clock timing is provided by either a series resonant crystal (3.579545 MHz 0.01%) connected across X1 and X2, or by an external TTL/CMOS clock driving X2 with AC coupling. In this latter case, X1 is left unconnected. See Fig. 10. 873.9 Hz clock output. This clock is used to implement external delay circuits etc.
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Semiconductor Control
Name Pin No. RS GS-K I/O Description
MSM6926/6946
LT
4
44
I
CC RS2
5 8
2 8
I I
Digital loop back test. During digital "High", any data sent on the XD pin will appear on the RD pin, and any data sent on the RS1 pin will immediately appear on the CS pin. Any data demodulated from the received carrier on the AIN pin will be the modulated data to implement the transmitted carrier. In this case, sending the transmitted carrier to the phone line depends on the CC, but never on RS1. During digital loop back test, the data on this pin becomes a control signal for sending the transmitted carrier to the phone line in place of RS1. When an external circuit gives the RS/CS delay time which is not within the device as required, this pin should be connected to the external circuit output. See Fig. 11. The fast carrier detection output. This pin is internally connected to the input of the built-in carrier detect delay circuit. When an external delay circuit provides the delay time which is not within the device as required, the CD1 should be connected to the external circuit input. See Fig. 11. When an external circuit gives the carrier detect delay time which is not within the device as required, this pin becomes the input pin for the external circuit output signal. In other cases (when using the delay time within the device, the data on the TS1 or TS2 is not digital "High"), this pin becomes the Carrier detect signal output. The RD1 data is demodulated data from the received carrier and the RD2 is the input of the following logic circuits referred to in Fig. 12. Usually, the RD1 data is input directly to RD2. In some cases, as input data to RD2, the data that is controlled by NCU (Network control unit) etc. may be required in stead of the RD1 data. These two pins are the output (CRD1) and inverting input (CDR2) of the buffer operational amplifier of which the noninverting input is connected to the built-in voltage reference, stabilized to variations in the supply voltage and temperature. See Fig. 13. An adequate carrier-detect level can be set by selecting the ratio of R8 to R9. Therefore, the loss in the received carrier level by phone-line transformer can be compensated by adjusting the ratio of R8 to R9. R8 + R9 should be greater than 50 kW. Answer/Originate mode select. During digital "High", the originate mode is selected. A low input selects the answer mode. This pin may be used for device tests only. During digital "High", the AO pin will be connected to receiving filter output instead of transmitting filter output. RS/CS delay and carrier detect delay options referred to chapter about timing characteristics are selected by TS1 and TS2 inputs. Be careful that each delay can not be individually selected. If another delay time than the ones within the device are required as an option, input a digital "High" to the TS1 and TS2 pin and implement the external delay circuits to obtain the desired delay characteristics. In this case, the CD2 pin becomes not only the input for the external circuit output signal, but also the Carrier detect output. See Fig. 11.
CD1
11
12
O
CD2
12
13
I/O
RD1 RD2
13 14
14 16
O I
CDR1
16
20
O
CDR2
17
21
I
M FT
22 23
31 32
I I
TS1
27
36
I
TS2
28
38
I
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MSM6926/6946
Input/Output
Pin No. RS GS-K 6 3
Name CS
I/O
Description Clear to send signal output. The digital "High" level indicates the "OFF" state and digital "Low" indicates the "ON" state. This output goes "Low" at the end of a delay (RS/CS delay) initiated when RS1 (Request to send) goes "Low". Request to send signal input. The digital "High" level indicates the "OFF" state. The digital "Low" level indicates the "ON" state and instructs the modem to enter the transmit mode. This input must remain "Low" for the duration of data transmission. "High" turns the transmitter off. This is digital data to be modulated and transmitted via AO. Digital "High" will be transmitted as "Mark". Digital "Low" will be transmitted as "Space". No signal appears at AO unless RS1 is "Low". Digital data demodulated from AIN is serially available at this output. Digital "High" indicates "Mark" and digital "Low" indicates "Space". For example, under the following condition, this output is forced to be "Mark" state because the data may be invalid. * When CD2 (Carrier detect) is in the "OFF" state. The SG1 and ST2 are built-in analog signal grounds. SG2 is used only for Carrier detect function. The DC voltage of SG1 is approximately 6 V, so the analog line interface must be implemented by AC coupling. See Fig. 9. To make impedance lower and ensure the device performance, it is necessary to put bypass capacitors on SG1 and SG2 in close physical proximity to the device. This is the input for the analog signal from the phone line. The modem extracts the information in this modulated carrier and converts it into a serial data stream for presentation at RD output. This analog output is the modulated carrier to be conditioned and sent over the phone line.
O
RS1
7
4
I
XD
9
9
I
RD
10
10
O
SG2 SG1
18 20
22 24
O O
AIN AO
21 25
26 34
I O
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Semiconductor
MSM6926/6946
ABSOLUTE MAXIMUM RATINGS
Parameter Power Supply Voltage Analog Input Voltage Digital Input Voltage Operating Temperature Storage Temperature *1 *2 *3 *1 *2 Symbol VA VD VIA VID Top TSTG
-- --
Condition Ta = 25C With respect to AG or DG
Rating -0.3 to 15 -0.3 to 7 -0.3 to VA + 0.3 -0.3 to VD + 0.3 0 to +70 -55 to 150
Unit
V
C
CDR2, AIN *3 X1, LT, CC, RS1, RS2, XD, CD2, RD2, M, FT, TS1, TS2 CD2 is I/O terminal
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RECOMMENDED OPERATING CONDITIONS
Parameter Power Supply Voltage Operating Temperature CRYSTAL R1 R2 R3 R4 R5 R6 R7 R8 R9 C0, C1 C2 C3 C4 C5 C6 Symbol VA VD AG, DG Top -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Condition With respect to AG With respect to DG -- -- -- Transformer impedance = 600 W Min. 10.8 4.75 -- 0 -- -- -- -- -- -- -- -- -- -- -- -- 22 0.01 -- -- Typ. 12.0 5.00 0 -- 3.579545 600 51 51 51 51 51 51 33 51 0.047 2.2 -- -- 10 10 Max. 13.2 5.25 -- 70 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- mF kW C MHz W V Unit
Application circuits using above conditions are provided in Fig. 8.
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Semiconductor
MSM6926/6946
ELECTRICAL CHARACTERISTICS
DC and Digital Interface Characteristics
(VA = 12 V 10%, VD = 5 V 5%, Ta = 0 to 70C) Parameter Power Supply Current Input Leakage Currnet Input Voltage Output Voltage *1 *1 *2 Symbol IA ID IIL IIH VIL VIH VOL VOH Condition Ordinary operation VI = 0 V VI = VD -- -- IOL = 1.6 mA IOH = 400 mA Min. -- -- -10 -10 0 2.2 0 0.8 VD Typ. 7.5 1.0 -- -- -- -- -- -- Max. 15.0 2.0 10 10 0.8 VD 0.4 VD V Unit mA mA
*3 *1 LT, CC, RS1, RS2, XD, CD2, RD2, M, FT, TS1, TS2 *3 *2 CLK, CS, RD, CD1, CD2, RD1 *3 CD2 is I/O terminal.
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Semiconductor Analog Interface Characteristics 1. MSM6926 Transmit carrier out (AO)
MSM6926/6946
(VA = 12 V 10%, VD = 5 V 5%, Ta = 0 to 70C) Parameter ORIGINATE MODE Carrier Frequency Mark 1 Space 0 Mark 1 Space 0 Symbol fOM fOS fCRYSTAL = 3.579545 MHz fAM fAS ROXA RLXA CLXA VOXA VOSX EOX -- -- -- -- -- C1 = 0.047 mF 1644 1844 -- 50 -- 4 VA -1 2 1650 1850 -- -- -- 6 VA 2 1656 1856 200 -- 100 8 VA +1 2 W kW pF *1 dBm V dB Condition Min. 974 1174 Typ. 980 1180 Max. 986 1186 Hz Unit
ANSWER MODE Carrier Frequency Output Resistance Load Resistance Load Capacitance Transmit Level Output Offset Voltage Out-of-Band Energy (Referred to Carrier Level)
Refer to Fig. 1
Receive carrier input (AIN)
Parameter Input Resistance Receive Signal Level Range Carrier Detect Level Carrier Detect Hysteresis ON Symbol RIRA VIRA VCD ON HYS OFF VCD OFF Condition -- -- R8 = 33 kW *2 R9 = 51 kW VCD ON - VCD OFF Min. 100 -48 -- -48 2 Typ. -- -- -- -- -- Max. -- -6 -43 -- -- dB *1 dBm Unit kW
Receive filter
Parameter Symbol ORIG. MODE ANS. MODE Condition 1600 to 1900 Hz 930 to 1230 Hz VAIN = -6 dBm Min. -- -- 50 Typ. 800 850 -- Max. -- ms -- -- dB Unit
Group Delay Distortion
DDL
Adjacent Channel Rejection
LAC
Notes: *1 0 dBm = 0.775 Vrms *2 The resistor values are typical
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Semiconductor
MSM6926/6946
02 0 -20 -40 -60 dB
4
6
8 10 12 14 16
kHz
Figure 1 MSM6926 Out-of-Band Energy Referred to Carrier Level (C1 = 0.047 mF)
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Semiconductor
MSM6926/6946
500 0 -10 -20 -30
1000
1500
Frequency (Hz)
Gain (dB)
-40 -50 -60 -70 -80
Figure 2 MSM6926 Low Band Filter
1500 0 -10 -20 -30 Gain (dB) -40 -50 -60 -70 -80
2000
Frequency (Hz)
Figure 3 MSM6926 High Band Filter
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Semiconductor
MSM6926/6946
2. MSM6946 Transmit carrier out (AO)
(VA = 12 V 10%, VD = 5 V 5%, Ta = 0 to 70C) Parameter ORIGINATE MODE Carrier Frequency Mark 1 Space 0 Mark 1 Space 0 Symbol fOM fOS fCRYSTAL = 3.579545 MHz fAM fAS ROXA RLXA CLXA VOXA VOSX EOX -- -- -- -- -- C1 = 0.047 mF 2219 2019 -- 50 -- 4 VA -1 2 2225 2025 -- -- -- 6 VA 2 2231 2031 200 -- 100 8 VA +1 2 W kW pF *1 dBm V dB Condition Min. 1264 1064 Typ. 1270 1070 Max. 1276 1076 Hz Unit
ANSWER MODE Carrier Frequency Output Resistance Load Resistance Load Capacitance Transmit Level Output Offset Voltage Out-of-Band Energy (Referred to Carrier Level)
Refer to Fig. 4
Receive carrier input (AIN)
Parameter Input Resistance Receive Signal Level Range Carrier Detect Level Carrier Detect Hysteresis ON Symbol RIRA VIRA VCD ON HYS OFF VCD OFF Condition -- -- R8 = 33 kW *2 R9 = 51 kW VCD ON - VCD OFF Min. 100 -48 -- -48 1.5 Typ. -- -- -- -- -- Max. -- -6 -43 -- -- dB *1 dBm Unit kW
Receive Filter
Parameter Symbol ORIG. MODE ANS. MODE Condition 1975 to 2275 Hz 1020 to 1320 Hz VAIN = -6 dBm Min. -- -- 50 Typ. 650 750 -- Max. -- ms -- -- dB Unit
Group Delay Distortion
DDL
Adjacent Channel Rejection
LAC
Notes: *1 0 dBm = 0.775 Vrms *2 The resistor values are typical
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Semiconductor
MSM6926/6946
0 0 -20 -40 -60
2
3.4 4
6
8 10 12 14 16
200
kHz
-25
15
dB/
OC
TAV
E
-55
dB
Figure 4 MSM6946 Out-of-Band Energy Referred to Carrier Level (C1 = 0.047 mF)
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Semiconductor
MSM6926/6946
500 0 -10 -20
1000
1500
2000
2500 Frequency (Hz)
Gain (dB)
-30 -40 -50 -60 -70 -80
Figure 5 MSM6946 Low Band Filter
1000 0 -10 -20
Gain (dB)
1500
2000
2500
3000 Frequency (Hz)
-30 -40 -50 -60 -70 -80
Figure 6 MSM6946 High Band Filter
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Semiconductor Demodulated Bit Characteristics
MSM6926/6946
(VA = 12 V 10%, VD = 5 V 5%, Ta = 0 to 70C) Parameter Peak Intersymbol Distortion Symbol ID Condition Back-to-back over input signal range -6 to -40 dBm. 511-bit test pattern. Back-to-back with 0.3 to 3.4 kHz flat noise. Receive signal level -25 dBm. 511-bit test pattern 5 dB S/N -- Min. -- Typ. 6 Max. -- Unit %
Bit Error Rate
BER
--
10-5
--
Timing Characteristics 1. MSM6926
(VA = 12 V 10%, VD = 5 V 5%, Ta = 0 to 70C) Parameter Symbol Condition RS1 = "0" AE CS = "0" RS1 = "1" AE CS = "1" TS2 TS1 0 TRC ON RS/CS Delay Time TRC OFF 0 1 1 * 0 CD/ON Delay Time TCD ON -- 0 1 1 0 CD/OFF Delay Time TCD OF -- 0 1 1 Soft Turn-OFF Time TST -- * 0 1 0 1 * 0 1 0 1 0 1 0 1 * Min. 395 25 345 Typ. 400 30 350 Max. 405 35 355 Unit
External delay timer 0 300 5 150 20 20 10 -- -- -- -- -- -- -- -- 10 0.5 320 20 170 70 70 40 -- ms
External delay timer
External delay timer
Refer to Fig. 7 Notes: *: Irrespective of I/O condition
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Semiconductor 2. MSM6946
MSM6926/6946
(VA = 12 V 10%, VD = 5 V 5%, Ta = 0 to 70C) Parameter Symbol Condition RS1 = "0" AE CS = "0" RS1 = "1" AE CS = "1" TS2 TS1 0 TRC ON RS/CS Delay Time TRC OFF 0 1 1 * 0 CD/ON Delay Time TCD ON -- 0 1 1 0 CD/OFF Delay Time TCD OF -- 0 1 1 Soft Turn-OFF Time TST -- * 0 1 0 1 * 0 1 0 1 0 1 0 1 * Min. 195 -- -- Typ. 200 + + Max. 205 -- -- Unit
External delay timer 0 100 -- -- 10 -- -- -- -- -- + + -- + + 10 0.5 120 -- -- 50 -- -- -- ms
External delay timer
External delay timer
Refer to Fig. 8 Notes: *: Irrespective of I/O condition +: Reserved
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Semiconductor
MSM6926/6946
TIMING DIAGRAM
RS1 CS TRCON TRCOFF
AO
TST
AIN
TCDON
TCDOFF
CD2
Figure 7 MSM6926/6946 Timing Diagram
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Semiconductor
MSM6926/6946
APPLICATION CIRCUIT
Phone Line C2 R1 R2 R5
- +
R3
R4
R6 R7
C0
- +
C1
DG or VD
VD
ORIG. MODE
ANS. MODE
Test Data
CS RS
XD RD
Notes: 1. 2. 3. 4.
The crystal should be wired in close physical proximity to the device. High level signals should not be routed next to low level signals. Bypass capacitors on VA, SG1, and SG2 should be as close to the device as possible. AG and DG should be connected as close to the system ground as possible. Figure 8 Application Circuit Using MSM6926RS/MSM6946RS 19/25
CD
Crystal 1 2 VD 3 4 5 Control 6 7 8 9 10 11 12 13 14
X1 X2 CLK LT CC CS RS1 RS2 XD RD CD1 CD2 RD1 RD2
TS2 28 TS1 27 VD 26 AO 25 VA 24 FT 23 + M 22 - AIN 21 SG1 20 C3 AG 19 C4 SG2 18 R8 CDR2 17 R9 CDR1 16 DG 15 DG AG
C5
VA
VD
+ -
C6
Semiconductor
MSM6926/6946
+6 dBm R5 AO 25 SG1 20 C3 AIN 21 AG 19 -6 dBm R6 C0 0 dBm -6 dBm R7 R4
- +
0 dBm R2 R1 C2 C1 600 W : 600 W Phone Line
R3
- +
Figure 9 MSM6926RS/MSM6946RS Application
C0, C1 C2 C3 R1
0.047 mF 2.2 mF 1 mF 600 W
R2 R3 R4 R5
51 kW 51 kW 51 kW (51 kW) Transmit signal level
R6 R7 R8 R9
(51 kW) Receive signal level 51 kW (33 kW) Carrier detect level 51 kW
Note: The signal level on the AIN pin should not exceed -6 dBm.
VD External Oscillator *1 GATE *2 X1 3.58 MHz External Oscillator Connection *1 TTL or Hi-Speed CMOS GATE *2 Left unconnected 200 pF X2
Figure 10
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Semiconductor
MSM6926/6946
RS
RS1 RS2 R * CK 4020
(A) VD VD
TS1 TS2
CD
Q Q CK D CD1
R
* CK 4020
(B) 873.9 Hz (C)
CD2
R
* CK 4020
CLK
(A) RS/CS delay, (B) CD/ON delay, (C) CD/OFF delay Note: Supply voltage equals VD for all gates. *: The desired delay can be realized by selecting the appropriate bits from 4020's outputs. The number of the bits is not always 3. Each delay can be set differently from built-in delays. Figure 11 External Delays Connection
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Semiconductor
MSM6926/6946
TS1 TS2 LT RS1 CS RS2
SW Control
RS/CS Delay CC XD RD Modulator Transmit Filter AO
CD2 CD1 CD ON CD OFF Delay DeModulator Carrier Detect RD2 RD1 Receive Filter AIN
Figure 12 Equivalent Logic Interface of the Integrated Modem
Carrier
Carrier Detect AC/DC Converter
COMP CD1 CDR1
SG2
+ -
R9 CDR2 R8 SG2 (R8 + R9) 50 kW
VREF
Figure 13 External Resistor Connection for the Setting of Carrier Detect Level
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Semiconductor
MSM6926/6946
PACKAGE DIMENSIONS
(Unit : mm)
DIP28-P-600-2.54
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more 4.30 TYP.
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Semiconductor
MSM6926/6946
(Unit : mm) QFP44-P-910-0.80-K
Mirror finish
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more 0.35 TYP.
Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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Semiconductor
MSM6926/6946
(Unit : mm) QFP44-P-910-0.80-2K
Mirror finish
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more 0.41 TYP.
Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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